This invention relates to a data storage arrangement having particular application to a speech synthesis system, wherein a plurality of memories form a set of memories defining a double table look-up in which address codes are utilized for specifying the speech data with a lowered bit rate to be applied to a speech synthesis circuit in the production of audible synthesized speech.
Several techniques are known in the prior art for digitizing human speech. For example, pulse code modulation, differential pulse code modulation, adaptive predictive coding, data modulation, channel vocoders, cepstrum, vocoders formant vocoders, voice excited vocoders and linear predictive coding techniques of speech digitalization are known. The techniques are briefly explained in "Voice Signals: Bit by Bit" on pages 28-34 of the Oct. 1973 issue of IEEE Spectrum.
In certain applications and particularly those in which the digitized speech is to be stored in a memory, most researchers tend to use the linear predictive coding technique because it produces very high quality speech using rather low data rates. Linear Predictive Coding systems usually make use of a multi-stage digital filter. In the past, the digital filter has typically been implemented by appropriately programming a large scale digital computer. However, in U.S. patent application Ser. No. 807,461, filed June 17, 1977, since abandoned in favor of continuation U.S. application Ser. No. 905,328 filed May 12, 1978, now U.S. Pat. No. 4,209,844 issued June 24, 1980, there is taught a particularly useful digital filter for a speech synthesis circuit, which digital filter may be implemented on an integrated circuit using standard MOS or equivalent technology. A theoretical discussion of linear predictive coding can be found in "Speech Analysis and Synthesis by Linear Prediction of the Speech Wave" at volume 50, number 2 (part 2) of The Journal of the Acoustical Society of America.
Disclosed herein is a talking learning aid which utilizes speech synthesis technology for producing human speech. A complete talking learning aid is disclosed, so, in addition to describing the speech synthesis circuits in detail, the details of the controller for the learning aid and the Read-Only-Memory devices used to store the digitized speech are also disclosed. Of course, those practicing the present invention may wish to practice the invention in conjunction with a talking learning aid, such as that described herein, other learning aids or any other application wherein the generation of human speech from digital data is desirable. Using the techniques described in the aforementioned U.S. Pat. No. 4,209,844 and the teachings disclosed herein will permit those desiring to make use of digital speech technology to do so with one, or a small number of relatively inexpensive integrated circuit devices.
The present invention relates to the manner in which speech data is accessed from data storage to be applied to a speech synthesis circuit in the production of audible synthesized speech. Insofar as is practical, it would be desirable to produce high quality synthesized speech having a natural sounding voice withou requiring an unduly high speech data rate to be processed through the speech synthesis circuit.
It is therefore one object of this invention to implement the accessing of specific speech data from memory with a reduction in the bit data rate as applied to a speech synthesis circuit in the synthesis of speech without sacrificing quality in the audible synthesized speech which is produced thereby.
It is another more specific object of this invention to provide a memory arrangement for a speech synthesis system wherein the memory arrangement involves a double table look-up as a means of lowering the speech data bit rate and which is relied upon in specifying the speech data to be delivered to a speech synthesis circuit of the system.
In accordance with the present invention, a memory arrangement having particular application to a speech synthesis system is provided wherein a plurality of memories form a set of memories which define a double table look-up for specifying the speech data to be applied to a speech synthesis circuit in the production of audible synthesized speech. The plurality of memories of the speech synthesis system include a first memory having speech data parameters of a fixed bit length stored therein. A second memory has encoded speech data stored therein as data addresses defining a speech parameter look-up table for identifying respective speech data parameters of increased bit length as stored in the first memory of the memory set such that the encoded speech data may be converted into the speech parameters of longer bit length when required by the speech synthesis circuit. The speech data is formed into data frames which define a plurality of data fields, with each data field corresponding to one memory location in the first memory. The speech data frames are stored in ordered sets in the second memory, and a third memory is provided with address data corresponding to the desired sets of speech data frames for identifying the specific speech data parameters to be applied to the speech synthesis circuit. Thus, the second and third memories comprise look-up tables and cooperate with the first memory in providing a double look-up table procedure for specifying, at a reduced bit rate, the speech data to be delivered to the speech synthesis circuit of the speech synthesis system.